1. Field of the Invention
The present invention relates in general to a test mode circuit for a memory device, and more particularly to a test mode circuit, for a memory device for, in a test mode, transforming information to be stored in the memory device and information being read from the memory device and selecting simultaneously information stored in cell arrays in the memory device, so as to grasp interferences between adjacent cells and between adjacent data bus lines in the memory device.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram of a conventional test mode circuit for a memory device. As shown in this drawing, the conventional memory device test mode circuit comprises a cell array section 20 having a plurality of cell arrays CA1-CAn for storing input data Din herein, a first switching section 10 for selecting one of test and normal modes and selecting one of the plurality of cell arrays CA1-CAn in the cell array section 20 in the normal mode, the input data Din being stored in only one of the plurality of cell arrays CA1-CAn selected by the first switching section 10 in the normal mode and being simultaneously stored in the plurality of cell arrays CA1-CAn in the test mode, a logic section 30 for inputting output data signals CAout from the plurality of cell arrays CA1-CAn in the cell array section 20 and discriminating whether the data signals CAout from the plurality of cell arrays CA1-CAn are the same, and a second switching section 40 for selecting one of the test and normal modes and selecting, as its output signal Dout, an output signal from the logic section 30 in the test mode and the data signal CAout from the selected one of the plurality of cell arrays CA1-CAn in the cell array section 20 in the normal mode.
The first switching section 10 includes a mode select switch SW11 having a movable contact c and fixed contacts a and b for inputting the input data Din, the movable contact c being connected to the fixed contact a in the normal mode and to the fixed contact b in the best mode, and a plurality of cell array select switches SW12, each having its one terminal connected to the fixed contact a of the switch SW11 and its other terminal connected to a corresponding one of the cell arrays CA1-CAn in the cell array section 20, for, in the normal mode, selecting one of the plurality of cell arrays CA1-CAn so that the input data Din through the contacts c and a of the switch SW11 is stored in the selected one of the plurality of cell arrays CA1-CAn.
The cell array section 20 consists of the plurality of cell arrays CA1-CAn, each of which includes a plurality of memory cells arranged in the form of matrix to store the input data applied through the switch SW11 in the switching section 10. Inputs of the plurality of cell arrays CA1-CAn are also connected directly to the fixed contact b of the switch SW11 in the switching section 10. In the normal mode, one of the plurality of cell arrays CA1-CAn is selected by a corresponding one of the cell array select switches SW12 in the switching section 10, thereby to store the input data. In the test mode, the input data is applied simultaneously to the plurality of cell arrays CA1-CAn through the switch SW11 in the switching section 10.
The logic section 30 includes first discriminating means 31 for inputting the output data signals CAout from the plurality of cell arrays CA1-CAn in the cell array section 20 and discriminating whether the data signals CAout from the plurality of cell arrays CA1-CAn are the same, and second discriminating means 32 for inputting inverted output data signals /CAout from the plurality of cell arrays CA1-CAn in the cell array section 20 and discriminating whether a different data signal is outputted from any one of the plurality of cell arrays CA1-CAn.
The first discriminating means 31 includes NAND and OR gates NA11 and OR11 for inputting the output data signals CAout from the plurality of cell arrays CA1-CAn in the cell array section 20 and a NAND gate NA12 for inputting output signals from the NAND and OR gates NA11 and OR11.
The second discriminating means 32 includes NAND and OR gates NA13 and OR12 for inputting the inverted output data signals /CAout from the plurality of cell arrays CA1-CAn in the cell array section 20 and an AND gate AN11 for inputting output signals from the NAND and OR gates NA13 and OR12.
The second switching section 40 includes a first cell array select switch SW13 having a movable contact c and a plurality of fixed contacts a, b, d, e . . . n for inputting the output data signals CAout from the plurality of cell arrays CA1-CAn in the cell array section 20, for selecting one of the output data signals CAout from the plurality of cell arrays CA1-CAn in the normal mode, a second cell array select switch SW14 having a movable contact c and a plurality of fixed contacts a, b, d, e . . . n for inputting the inverted output data signals /CAout from the plurality of cell arrays CA1-CAn in the cell array section 20, for selecting one of the inverted output data signals /CAout from the plurality of cell arrays CA1-CAn in the normal mode, a first mode select switch SW15 having a movable contact c and fixed contacts a and b, the movable contact c being, in the normal mode, connected to the fixed contact a to select the output data signal from the cell array selected by the switch SW13 and, in the test mode, connected to the fixed contact b to select an output signal from the first discriminating means 31 in the logic section 30, and a second mode select switch SW16 having a movable contact c and fixed contacts a and b, the movable contact c being, in the normal mode, connected to the fixed contact a to select the inverted output data signal from the cell array selected by the switch SW14 and, in the test mode, connected to the fixed contact b to select an output signal from the second discriminating means 32 in the logic section 30. The second switching section 40 also includes a first N type MOS transistor MN11 for outputting the output data signal from the cell array section 20 or the output signal from the first discriminating means 31 in the logic section 30 in response to the operation of the switch SW15, and a second N type MOS transistor MN12 for outputting the inverted output data signal from the cell array section 20 or the output signal from the second discriminating means 32 in the logic section 30 in response to the operation of the switch SW16.
The operation of the conventional memory device test mode circuit with the above-mentioned construction will hereinafter be described.
In the normal mode, the movable contact c of the mode select switch SW11 in the first switching section 10 is connected to the fixed contact a thereof in response to an external control signal and one of the plurality of cell array select switches SW12 in the first switching section 10 is selected, thereby to select a corresponding one of the plurality of cell arrays CA1-CAn in the cell array section 20. Input data Din is stored in the memory cell of the selected cell array.
The data stored in this manner in the selected cell array CA is sensed by the second switching section 40 for its output. At this time, in the second switching section 40, the movable contacts c of the cell array select switches SW13 and SW14 are connected to the respective ones of the fixed contacts a, b, d, e . . . n thereof and the movable contacts c of the mode select switches SW15 and SW16 are connected to the fixed contacts a thereof, respectively.
Accordingly, the output signal CAout from the selected cell array CA is applied to a gate terminal of the N type MOS transistor MN11 through the switches SW13 and SW15, thereby allowing the data Dout to be outputted from the N type MOS transistor MN11. On the other hand, the inverted output signal /CAout from the selected cell array CA is applied to a gate terminal of the N type NOS transistor MN12 through the switches SW14 and SW16, thereby allowing the data Dout to be outputted from the N type MOS transistor MN12.
In the test mode, the movable contact c of the mode select switch SW11 in the first switching section 10 is connected to the fixed contact b thereof in response to an external control signal, to apply the input data Din simultaneously to the plurality of cell arrays CA1-CAn in the cell array section 20. The input data Din is stored simultaneously in shortened addresses of the cell arrays CA1-CAn.
The data stored in this manner in the cell arrays CA1-CAn is sensed by the logic section 30 for its output. At this time, in the case where the same data of logic 1 or 0 are outputted from the plurality of CA1-CAn, the output of the NAND gate NA12 of the first discriminating means 31 in the logic section 30 is logic 1. Since the movable contact C of the mode select switch SW15 is connected to the fixed contact b thereof in the test mode, the output of the first discriminating means 31 is applied to the gate terminal of the MOS transistor MN11 through the switch 15. As a result, the MOS transistor MN11 is tutored on, thereby causing the output data Dout to become logic 1.
On the other hand, when at least one different data is outputted from the plurality of cell arrays CA1-CAn due to a failure of the memory device, the output of the AND gate AN11 of the second discriminating means 32 in the logic section 30 becomes logic 1. The logic 1 signal is applied to the gate terminal of the MOS transistor MN12 through the switch SW16. As a result, the MOS transistor MN12 is turned on, thereby causing the output data Dout to become logic 0.
Accordingly, the presence of a failure of the memory device is tested on the basis of the logical state of the output data Dout.
The method of testing the memory device as mentioned above is generally classified into a method of repeatedly performing the above-mentioned operation of selecting the memory cells in the plurality of cell arrays, storing the data simultaneously in the memory cells and reading the data and a method of repeatedly performing an operation of selecting a plurality of adjacent memory cells in one of the plurality of cell arrays, storing the data simultaneously in the memory cells and reading the data.
However, the conventional memory device test mode circuit has a disadvantage, in that, in the case where it selects the plurality of adjacent memory cells in one of the plurality of cell arrays for the test of the memory device, it cannot grasp interferences between the adjacent cells and between adjacent data bus lines in the memory device, since the information to be stored in the memory device is inputted simultaneously through only the one terminal in the test mode.